Sutherland Stuart <br/><br/>
RTL modeling with system verilog for simulation and synthesis  Using system verilog for ASIC and FPGA design 

 - Oregon  "Sutherland HDL, Inc"  2021 
<br/><br/><label>Subjects--Topical Terms: </label><br/>ETC_ELECTRONICS
<br/><br/><label>Dewey Class. No.: </label>621.392